Instruction Set of 8086

8086 Instruction Set

These marks are used to show the state of the flags:

1 - instruction sets this flag to 1.
0 - instruction sets this flag to 0.
r - Flag value depends on result of the instruction.
? - Flag value is undefined (maybe 1 or 0).

Instruction	Operands	Description
AAA	No operands	ASCII Adjust after Addition. Corrects result in AH and AL after addition when working with BCD values. C Z S O P A r ? ? ? ? r
AAD	No operands	ASCII Adjust before Division. Prepares two BCD values for division. C Z S O P A ? r r ? r ?
AAM	No operands	ASCII Adjust after Multiplication. Corrects the result of multiplication of two BCD values. C Z S O P A ? r r ? r ?
AAS	No operands	ASCII Adjust after Subtraction. Corrects result in AH and AL after subtraction when working with BCD values. C Z S O P A r ? ? ? ? r
ADC	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Add with Carry. C Z S O P A r r r r r r
ADD	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Add. C Z S O P A r r r r r r
AND	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Logical AND between all bits of two operands. Result is stored in operand1. C Z S O P 0 r r 0 r
CALL	procedure name label 4-byte address	Transfers control to procedure, return address is (IP) is pushed to stack. 4-byte address may be entered in this form: 1234h:5678h, first value is a segment second value is an offset (this is a far call, so CS is also pushed to stack). C Z S O P A unchanged
CBW	No operands	Convert byte into word. C Z S O P A unchanged
CLC	No operands	Clear Carry flag. C 0
CLD	No operands	Clear Direction flag. SI and DI will be incremented by chain instructions: CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW. D 0
CLI	No operands	Clear Interrupt enable flag. This disables hardware interrupts. I 0
CMC	No operands	Complement Carry flag. Inverts value of CF. C r
CMP	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Compare. C Z S O P A r r r r r r
CMPSB	No operands	Compare bytes: ES:[DI] from DS:[SI]. C Z S O P A r r r r r r
CMPSW	No operands	Compare words: ES:[DI] from DS:[SI]. C Z S O P A r r r r r r
CWD	No operands	Convert Word to Double word.
DAA	No operands	Decimal adjust After Addition. Corrects the result of addition of two packed BCD values. C Z S O P A r r r r r r
DAS	No operands	Decimal adjust After Subtraction. Corrects the result of subtraction of two packed BCD values. C Z S O P A r r r r r r
DEC	REG memory	Decrement. Z S O P A r r r r r CF - unchanged!
DIV	REG memory	Unsigned divide. C Z S O P A ? ? ? ? ? ?
HLT	No operands	Halt the System. C Z S O P A unchanged
IDIV	REG memory	Signed divide. C Z S O P A ? ? ? ? ? ?
IMUL	REG memory	Signed multiply. C Z S O P A r ? ? r ? ? CF=OF=0 when result fits into operand of IMUL.
IN	AL, im.byte AL, DX AX, im.byte AX, DX	Input from port into AL or AX. Second operand is a port number. If required to access port number over 255 - DX register should be used. C Z S O P A unchanged
INC	REG memory	Increment. Z S O P A r r r r r CF - unchanged!
INT	immediate byte	Interrupt numbered by immediate byte (0..255). C Z S O P A I unchanged 0
INTO	No operands	Interrupt 4 if Overflow flag is 1.
IRET	No operands	Interrupt Return. C Z S O P A popped
JA	label	Short Jump if first operand is Above second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JAE	label	Short Jump if first operand is Above or Equal to second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JB	label	Short Jump if first operand is Below second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JBE	label	Short Jump if first operand is Below or Equal to second operand (as set by CMP instruction). Unsigned.    C Z S O P A unchanged
JC	label	Short Jump if Carry flag is set to 1. C Z S O P A unchanged
JCXZ	label	Short Jump if CX register is 0. C Z S O P A unchanged
JE	label	Short Jump if first operand is Equal to second operand (as set by CMP instruction). Signed/Unsigned. C Z S O P A unchanged
JG	label	Short Jump if first operand is Greater then second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JGE	label	Short Jump if first operand is Greater or Equal to second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JL	label	Short Jump if first operand is Less then second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JLE	label	Short Jump if first operand is Less or Equal to second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JMP	label 4-byte address	Unconditional Jump. Transfers control to another part of the program. 4-byte address may be entered in this form: 1234h:5678h, first value is a segment second value is an offset. C Z S O P A unchanged
JNA	label	Short Jump if first operand is Not Above second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JNAE	label	Short Jump if first operand is Not Above and Not Equal to second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JNB	label	Short Jump if first operand is Not Below second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JNBE	label	Short Jump if first operand is Not Below and Not Equal to second operand (as set by CMP instruction). Unsigned. C Z S O P A unchanged
JNC	label	Short Jump if Carry flag is set to 0. C Z S O P A unchanged
JNE	label	Short Jump if first operand is Not Equal to second operand (as set by CMP instruction). Signed/Unsigned.    C Z S O P A unchanged
JNG	label	Short Jump if first operand is Not Greater then second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JNGE	label	Short Jump if first operand is Not Greater and Not Equal to second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JNL	label	Short Jump if first operand is Not Less then second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JNLE	label	Short Jump if first operand is Not Less and Not Equal to second operand (as set by CMP instruction). Signed. C Z S O P A unchanged
JNO	label	Short Jump if Not Overflow. C Z S O P A unchanged
JNP	label	Short Jump if No Parity (odd). Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.    C Z S O P A unchanged
JNS	label	Short Jump if Not Signed (if positive). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions. C Z S O P A unchanged
JNZ	label	Short Jump if Not Zero (not equal). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions. C Z S O P A unchanged
JO	label	Short Jump if Overflow. C Z S O P A unchanged
JP	label	Short Jump if Parity (even). Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.    C Z S O P A unchanged
JPE	label	Short Jump if Parity Even. Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions. C Z S O P A unchanged
JPO	label	Short Jump if Parity Odd. Only 8 low bits of result are checked. Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions. C Z S O P A unchanged
JS	label	Short Jump if Signed (if negative). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions. C Z S O P A unchanged
JZ	label	Short Jump if Zero (equal). Set by CMP, SUB, ADD, TEST, AND, OR, XOR instructions.   C Z S O P A unchanged
LAHF	No operands	Load AH from 8 low bits of Flags register. C Z S O P A unchanged
LDS	REG, memory	Load memory double word into word register and DS. C Z S O P A unchanged
LEA	REG, memory	Load Effective Address. C Z S O P A unchanged
LES	REG, memory	Load memory double word into word register and ES. C Z S O P A unchanged
LODSB	No operands	Load byte at DS:[SI] into AL. Update SI. C Z S O P A unchanged
LODSW	No operands	Load word at DS:[SI] into AX. Update SI. C Z S O P A unchanged
LOOP	label	Decrease CX, jump to label if CX not zero. C Z S O P A unchanged
LOOPE	label	Decrease CX, jump to label if CX not zero and Equal (ZF = 1). C Z S O P A unchanged
LOOPNE	label	Decrease CX, jump to label if CX not zero and Not Equal (ZF = 0). C Z S O P A unchanged
LOOPNZ	label	Decrease CX, jump to label if CX not zero and ZF = 0. C Z S O P A unchanged
LOOPZ	label	Decrease CX, jump to label if CX not zero and ZF = 1. C Z S O P A unchanged
MOV	REG, memory memory, REG REG, REG memory, immediate REG, immediate SREG, memory memory, SREG REG, SREG SREG, REG	Copy operand2 to operand1. The MOV instruction cannot: ·                     Set the value of the CS and IP registers. ·                     Copy value of one segment register to another segment register (should copy to general register first). ·                     Copy immediate value to segment register (should copy to general register first). C Z S O P A unchanged
MOVSB	No operands	Copy byte at DS:[SI] to ES:[DI]. Update SI and DI. C Z S O P A unchanged
MOVSW	No operands	Copy word at DS:[SI] to ES:[DI]. Update SI and DI. C Z S O P A unchanged
MUL	REG memory	Unsigned multiply. C Z S O P A r ? ? r ? ? CF=OF=0 when high section of the result is zero.
NEG	REG memory	Negate. Makes operand negative (two's complement). C Z S O P A r r r r r r
NOP	No operands	No Operation. C Z S O P A unchanged
NOT	REG memory	Invert each bit of the operand. C Z S O P A unchanged
OR	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Logical OR between all bits of two operands. Result is stored in first operand. C Z S O P A 0 r r 0 r ?
OUT	im.byte, AL im.byte, AX DX, AL DX, AX	Output from AL or AX to port. First operand is a port number. If required to access port number over 255 - DX register should be used. C Z S O P A unchanged
POP	REG SREG memory	Get 16 bit value from the stack. C Z S O P A unchanged
POPF	No operands	Get flags register from the stack. C Z S O P A popped
PUSH	REG SREG memory immediate	Store 16 bit value in the stack. Note: PUSH immediate works only on 80186 CPU and later! C Z S O P A unchanged
PUSHF	No operands	Store flags register in the stack. C Z S O P A unchanged
RCL	memory, immediate REG, immediate memory, CL REG, CL	Rotate operand1 left through Carry Flag. The number of rotates is set by operand2. When immediate is greater then 1, assembler generates several RCL xx, 1 instructions because 8086 has machine code only for this instruction (the same principle works for all other shift/rotate instructions). C O r r OF=0 if first operand keeps original sign.
RCR	memory, immediate REG, immediate memory, CL REG, CL	Rotate operand1 right through Carry Flag. The number of rotates is set by operand2. C O r r OF=0 if first operand keeps original sign.
REP	chain instruction	Repeat following MOVSB, MOVSW, LODSB, LODSW, STOSB, STOSW instructions CX times. Z r
REPE	chain instruction	Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Equal), maximum CX times. Z r
REPNE	chain instruction	Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not Equal), maximum CX times. Z r
REPNZ	chain instruction	Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 0 (result is Not Zero), maximum CX times. Z r
REPZ	chain instruction	Repeat following CMPSB, CMPSW, SCASB, SCASW instructions while ZF = 1 (result is Zero), maximum CX times. Z r
RET	No operands or even immediate	Return from near procedure. C Z S O P A unchanged
RETF	No operands or even immediate	Return from Far procedure. C Z S O P A unchanged
ROL	memory, immediate REG, immediate memory, CL REG, CL	Rotate operand1 left. The number of rotates is set by operand2. C O r r OF=0 if first operand keeps original sign.
ROR	memory, immediate REG, immediate memory, CL REG, CL	Rotate operand1 right. The number of rotates is set by operand2. C O r r OF=0 if first operand keeps original sign.
SAHF	No operands	Store AH registers into low 8 bits of Flags register. C Z S O P A r r r r r r
SAL	memory, immediate REG, immediate memory, CL REG, CL	Shift Arithmetic operand1 Left. The number of shifts is set by operand2. C O r r OF=0 if first operand keeps original sign.
SAR	memory, immediate REG, immediate memory, CL REG, CL	Shift Arithmetic operand1 Right. The number of shifts is set by operand2. C O r r OF=0 if first operand keeps original sign.
SBB	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Subtract with Borrow. C Z S O P A r r r r r r
SCASB	No operands	Compare bytes: AL from ES:[DI]. C Z S O P A r r r r r r
SCASW	No operands	Compare words: AX from ES:[DI]. C Z S O P A r r r r r r
SHL	memory, immediate REG, immediate memory, CL REG, CL	Shift operand1 Left. The number of shifts is set by operand2. C O r r OF=0 if first operand keeps original sign.
SHR	memory, immediate REG, immediate memory, CL REG, CL	Shift operand1 Right. The number of shifts is set by operand2. C O r r OF=0 if first operand keeps original sign.
STC	No operands	Set Carry flag. C 1
STD	No operands	Set Direction flag. SI and DI will be decremented by chain instructions: CMPSB, CMPSW, LODSB, LODSW, MOVSB, MOVSW, STOSB, STOSW. D 1
STI	No operands	Set Interrupt enables flag. This enables hardware interrupts. I 1
STOSB	No operands	Store byte in AL into ES:[DI]. Update DI. C Z S O P A unchanged
STOSW	No operands	Store word in AX into ES:[DI]. Update DI. C Z S O P A unchanged
SUB	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Subtract. C Z S O P A r r r r r r
TEST	REG, memory memory, REG REG, REG memory, immediate REG, immediate	Logical AND between all bits of two operands for flags only. These flags are affected: ZF, SF, PF. Result is not stored anywhere. C Z S O P 0 r r 0 r
XCHG	REG, memory memory, REG REG, REG	Exchange values of two operands.
XLATB	No operands	Translate byte from table. Copy value of memory byte at DS:[BX + unsigned AL] to AL register. C Z S O P A unchanged
XOR	REG, memory memory, REG REG, REG memory, immediate	Logical XOR (Exclusive OR) between all bits of two operands. Result is stored in first operand. C Z S O P A 0 r r 0 r ?